1. Field of Invention
The present invention relates to semiconductor integrated circuits, and more particularly to a frequency locking system.
2. Description of Related Arts
The conventional digital frequency locking system usually adopts the locking manner of: dividing a unit data width into four sub-intervals by a two-phase quadrature clock edge; sampling the two-phase quadrature clock edge with a data edge, so as to obtain information about which specific sub-interval the data edge falls into, and recording the sampled information; comparing the sampled information with previous sampled information, and detecting out frequency difference information if the sub-interval where the data edge falls changes continuously. The locking manner has following defects. Firstly, when the data edge samples the clock, high-speed data require a tight sequence of a sampler. Secondly, the quadrature clock edge divides the unit data width into the four sub-intervals; the frequency detection requires the continuous changes of the sub-interval, so an absolute value of an error between an initial frequency and a reference frequency must be smaller than 25%, which leads to a small locking range for the frequency to fall into. Thirdly, the edge locking and determination manner is liable to induce locking a frequency multiplying point.
Thus it is necessary to provide an improved frequency locking system to overcome the above defects.